Show HN: Write, simulate and synthesize VHDL/Verilog in the browser

Category: devtools

Tags: vhdl, verilog, eda, browser-based, hardware-design

Score: 6.0/10 (Innovation: 7, Technical: 6, Documentation: 3, Utility: 5)

RisingEdge.pro is a browser-based platform for writing, simulating, and synthesizing VHDL/SystemVerilog using a real EDA toolchain, with interactive waveforms and guided lessons. It lowers the barrier to hardware design by eliminating setup and licensing hurdles, making it accessible for learners and educators.

Target audience: hardware engineers, students, educators

Repository: https://risingedge.pro

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